1. Field of the Invention
An object of the present invention is an EEPROM (electrically erasable and programmable read-only memory) provided with a memory cell with capacitive memorizing. It also relates to a method for the reading of a memory cell such as this. It can be applied to the field of non-volatile memories. This field corresponds to that of memory cells, each provided with a floating-gate transistor as a memorizing element. The aim of the invention is to increase the density of integration of these cells on one and the same semiconductor substrate. The cells of the invention enable the storage, in a lasting way, of one binary logic state (1 or 0) or another, even if the supply of the electronic circuit to which they are connected is cut off. The following are the advantages of the cells of the invention:
very small geometrical size of the cell, whence the possibility of making very dense memories; PA1 zero consumption of current in reading and programming modes, which is very useful for contactless chip cards or in space-related applications; PA1 the use of standard existing manufacturing technologies, namely those of cells known as EEPROM or flash-EEPROM cells; PA1 the possibility of writing a 0 or a 1 in only one cell at a time instead of having to process an entire block: PA1 greater reading speed through reading at zero current. PA1 the bit lines are precharged at a voltage, the value of which is at least equal to the absolute value of the conduction threshold of the cell for a programmed state to minimize the capacitances of the bit lines; PA1 the bit line and the word line concerned by the cell to be read are selected, and PA1 the voltage remaining on the selected bit line is compared with a reference voltage, and the state read is deduced therefrom.
2. Description of the Prior Art
There are known non-volatile memory cells with a floating-gate transistor. Electrical charges are stored in this floating gate. The transistor is on or off depending on the memorized state, depending on the number of charges stored. These cells are of three types. There are the EPROM cells, the EEPROM cells and the flash-EEPROM cells. With an EPROM cell, the floating gate may be charged with electrons or it may have its electrons discharged. The floating-gate transistor is on when the floating gate has its electrons discharged. The integration density of these cells is good, but the programming current (to inject the electrons into the floating gate) is substantial. The programming voltage should therefore be given from the exterior of the integrated circuit which comprises the memory. These cells are not electrically erasable: they should be erased by an ultraviolet radiation. This furthermore prompts the erasure of the entire memory and not that of only one cell at a time. For the reading of a cell such as this, as for the reading of the cells of the other two types, a measurement is made of the intensity of a so-called reading current flowing through this transistor.
With an EEPROM memory, the access to a cell should be set up through an access transistor: the integration density is thereby reduced by four. The gate oxide interposed between the floating gate and the conduction channel of the transistor is far smaller than for an EPROM cell. It is of the order of 7 nm. The floating-gate transistor is on when the floating gate is charged with holes. It goes off when the floating gate is charged with electrons. The cells are programmable and erasable by blocks.
The flash-EEPROM cells have a same type of technological architecture as the EEPROM cells, but without any access transistor. Their integration density is greater. However, it is difficult to devise the manufacturing method: during the programming, the programming time is very lengthy (some seconds) and the programming threshold voltages have to be very precisely controlled. The cell consumes current in erasure mode and in reading mode.
The gates of all these cells are preferably one on top of the another, but it is quite possible to envisage the making of a buried control gate surmounted by the floating gate. The latter then overhangs the edge of a drain region of a transistor, or quite simply a doped region. This will also be the case for the cells of the invention even though, to simplify matters, the present invention relates more specifically to stacked structures.
A cell, in the prior art or in the invention, is said to be programmed if it has received holes on its floating gate. It is said to be erased if it has received electrons. When it is programmed, its conduction threshold is negative: for example, the value of this threshold is -2 V. Thus, this cell would become conductive if the voltage applied to its control gate of its transistor were to be greater than -2 V, while it is biased by 5 V at its drain and 0 V at its source. When it is erased, its conduction threshold is positive, for example 4 V, under the same conditions as above. The conduction threshold is therefore greater in the erased state than in the programmed state.